With the remarkable advances in semiconductor technologies, the electronics industry has been through a very rapid revolution from thick to thin films and to ever increasing miniaturization. Semiconductor packaging, which is the science of establishing interconnections with the semiconductor devices to form circuits, has been developed concurrently with the rapid advances in the semiconductor and electronics industries. The main purpose of packaging is to ensure that the semiconductor devices and interconnections are packaged efficiently and reliably.
As miniaturization and high performance are demanded in electronic products (such as cell phones, laptops, personal digital assistants (PDAs) and the like), high-density integrated circuits are frequently arranged within compact semiconductor packages such as a flip-chip package and a ball grid array (BGA) package. For example, in BGA package, an array of solder balls is configured so that each solder ball contacts a corresponding ball-pad to define a “ball-grid” array. Electronic devices with ball-grid arrays are generally high capacity packages that have higher pin counts than conventional chip packages that use a lead frame.
FIGS. 1A to 1F illustrate schematic cross-sectional views of a conventional method of forming a solder bump. As shown in 1A, a wafer 110 is provided with an active surface 112, and the wafer also has a passivation layer 114 and a plurality of bonding pads 116. It is noted that the passivation layer 114 is patterned to expose the bonding pads 116. Furthermore, a metallic layer 120 is formed to cover the passivation layer 114 and the bonding pads 116. The metallic layer 120 is actually an interface between the bonding pads 116 and a subsequently formed conductive pillar 140 (see FIG. 1C).
Referring to FIGS. 1B to 1F, a patterned mask layer 130 is formed over the metallic layer 120 with a plurality of openings 132 located on top of the bonding pads 116 and at least a portion of the metallic layer 120 is exposed. An electroplating operation is performed to deposit conductive materials into the opening 132, and the exposed metallic layer 120 is used as a seed layer. A conductive pillar 140 is thus formed to partially fill the opening 132, and a cylindrical solder cap 150 is formed by conductive an electroplating operation or a printing operation. The mask layer 130 and a portion of the metallic layer 120 are removed, and a bump with a solder cap structure 160 is formed. It is noted that the solder cap may have a cylindrical shape 150 or a hemispherical shape 150a. 
One disadvantage of conventional bump with solder cap formation is that only pure tin (Sn) or Sn (tin)/Ag (silver) alloy could be used in the electroplating operation. Practically, it is very difficult to perform electroplating for other different solder alloys. Furthermore, the volume of the solder cap during the electroplating operation is difficult to control, meaning that the height of each solder cap is not as uniform as desired. Also, the throughput for electroplating is much lower than solder “ball drop” technique. Therefore, there is a need for a new and improved method of forming solder cap bumps with more flexibility in the formation process, and the volume of the solder cap thereof can be more easily and precisely controlled.